A 158‐μ W, 100.6‐dB SNDR Audio Second‐Order Delta‐Sigma Modulator Using Two‐Stage Feedforward FIA and Bi‐ADWA

This paper presents a low‐power, high‐linearity, fully dynamic discrete‐time delta‐sigma modulator suitable for audio applications. Building upon the established bi‐directional advancing data weighted averaging (Bi‐ADWA) algorithm, this modulator effectively addresses the unit nonlinearity issues caused by manufacturing deviations in multi‐bit digital‐to‐analog converter (DAC) and suppresses the tonal distortion inherent in traditional DWA schemes. Its key contribution lies in extending the Bi‐ADWA algorithm to a 4‐bit quantizer, demonstrating that the algorithm can be scaled to higher resolutions. Furthermore, this paper integrates a two‐stage feedforward floating inverting amplifier (FIA), which alleviates the high power consumption of static operational amplifiers while overcoming the gain limitations of single‐stage FIAs. The modulator was implemented using a 180‐nm CMOS process. Post‐layout simulation results indicate a power consumption of 158 W at a 1.8‐V supply voltage, achieving a signal‐to‐noise‐and‐distortion ratio (SNDR) of 100.6 dB and a spurious‐free dynamic range (SFDR) of 107.8 dB. The active core area is 0.44 mm 2 . These results validate the effectiveness of the proposed architecture and provide a reliable solution for enhancing the linearity of multi‐bit DACs.