Comment on “Enhanced DSP Architecture for Small Floating‐Point Based Deep Learning Accelerators on FPGAs”

An enhanced FPGA DSP architecture integrates low-bit floating-point-to-fixed-point conversion with efficient INT8 DSP packing, reducing LUT and DSP resource requirements in reported deep-learning workloads. The results demonstrate improved computational density while highlighting the importance of area, operating frequency, and resource utilization in evaluating low-precision FPGA accelerators.