A 6.2‐bit Charge‐Sharing Noise‐Shaping SAR ADC Using Flexible Oxide TFT Technology

This work presents a 5‐bit successive approximation register (SAR) analog‐to‐digital converter (ADC) implemented using unipolar, single‐gate amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs). The circuit was fabricated on a 30 m‐thick polyimide substrate with an active area of 6.53 mm. The proposed ADC architecture employs the charge‐sharing (CS) principle to achieve low power consumption through passive switching. In addition, noise shaping (NS) is incorporated to enhance the effective number of bits (ENOB) and thereby improve the overall figure‐of‐merit (FoM). With NS, the ADC achieves an ENOB of 6.22 bits over a signal bandwidth of 346 Hz with an OSR of 4. The ADC operates at a sampling frequency of 2.77 kHz and consumes 2.48 mW of power from a 4 V supply under ambient conditions. Considering the effective signal bandwidth, the ADC achieves a Walden FoM () of 48.2 nJ/conversion‐step. To the best of our knowledge, this is the first demonstration of a CS‐NS‐based SAR ADC architecture using flexible unipolar TFT technology. Owing to the combination of passive CS conversion and first‐order NS, the proposed ADC is suitable for flexible biomedical applications.