Integration of Reconfigurable p‐Bit and 1R Crossbar Array for Memristive Probabilistic Computing

Probabilistic computing has emerged as an efficient paradigm for solving complex problems with high dimensionality and massive combinatorial search spaces. In particular, combinatorial optimization problems (COPs) can be mapped onto energy-based models described by an interaction (J) matrix and bias (h) vector. In hardware implementations, these parameters can be physically encoded as conductance values in a resistive crossbar array (CBA), while probabilistic bits (p-bits) provide a stochastic update of the energy state based on a weighted-sum operation across the CBA. Here, we present a memristive probabilistic computing system that integrates volatile memristors as p-bits and non-volatile memristors organized in a selector-less 1R CBA for representing the J matrix and h vector. The volatile memristors perform stochastic conductive filament formation and rupture to generate reconfigurable probabilistic outputs, while the non-volatile memristors form a nanocluster-based conductive path that enable reliable array operation without additional selector devices. The integrated system is experimentally validated through reversible AND and NAND gate operations in both forward and inverse modes. Furthermore, the scalability and generality of the proposed architecture were evaluated through simulation of a 2-bit binary multiplier operation. This work presents a practical and scalable framework for fully hardware-based probabilistic computing using memristive technologies.