Hardware Accountability for Energy-Efficient Stream-Oriented Data-Plane Processing in 5G/6G Edge Telecommunication Nodes

Continuous stream-oriented data-plane processing in 5G/6G edge nodes increases the energy and latency cost of CPU-centered execution. This paper studies this boundary on an Intel Cyclone V SoC FPGA and proposes Hardware Accountability: a partitioning discipline in which Linux performs supervisory control while high-rate payload processing remains in programmable logic. The evaluation uses the Strumok stream cipher, adopted as the Ukrainian national standard DSTU 8845:2019, as a secure fronthaul/payload workload with XOR- and shift-dominated logic. On the evaluated USB 2.0/Cortex-A9/Linux path, the software-driven stream approaches saturation near 20 MSPS. In contrast, the RTL core reaches 9.6 Gbps at 150 MHz and occupies less than 6% of the available logic. Quartus Prime vectorless power analysis estimates 24.00 mW dynamic power for the RTL computational core, corresponding to approximately 2.5 pJ/bit. Control-plane measurements show P99 orchestration jitter below 1 ms under Spatial Isolation, conservative full context reloads near 1290 per second, and more than 7200 shadow-register context/state update operations per second. A design-space exploration then projects an 83.2 Gbps multi-core data path when external DDR traffic is avoided through internal stream aggregation and elastic buffering.