A high-performance dataflow-driven 2-D transform architecture for versatile video coding

The Versatile Video Coding (VVC) standard incorporates Multiple Transform Selection (MTS), which improves compression efficiency but also leads to increased computational complexity and irregular dataflow, making efficient real-time hardware implementation challenging. To resolve this, our work proposes a high-performance streaming 2-D transform hardware architecture. It achieves a deterministic steady-state throughput using Diagonal-Rotation Banked Dual-Buffer (DR-BDB) transpose, characterized by conflict-free banked memory organization. The proposed architecture supports transform block sizes from 4 x 4 to 64 x 64. The transform architecture simulation results confirm deterministic latency and sustained streaming behaviour. The obtained synthesis results demonstrate the effectiveness of system-level dataflow co-design for high-throughput. This design achieves a processing rate of up to 370 fps for Ultra High Definition (UHD 3840x2160) video at a maximum frequency of 293.72 MHz. This makes the architecture well-suited for high-performance video processing applications.