Side-Channel Leakage Assessment of an FPGA-Based AES-256 Implementation Using TVLA

This paper presents an experimental evaluation of side-channel leakage in an FPGA-based implementation of the AES-256 encryption algorithm operating in ECB mode, with a focus on identifying data-dependent information leakage through power consumption and electromagnetic emissions. The implementation was deployed on a Xilinx Artix-7 FPGA using the ChipWhisperer CW305 platform, while measurements were acquired with the ChipWhisperer Husky system under controlled laboratory conditions. The analysis follows the Test Vector Leakage Assessment methodology in accordance with ISO/IEC 17825, using Welch’s t-test to compare trace sets obtained from fixed and random input data. A dataset of 20,000 traces per configuration was collected, with careful synchronization, interleaving, and preprocessing to ensure statistical reliability. The results show multiple instances where the t-statistic exceeds the threshold of |t| > 4.5 within the defined region of interest, indicating significant leakage. In particular, 84 leakage points were detected in the power consumption channel and 10 in the electromagnetic channel. These findings demonstrate that the evaluated implementation does not satisfy the resistance criteria defined by the standard and remains vulnerable to side-channel analysis, highlighting the need for appropriate countermeasures in FPGA-based cryptographic designs.