An Efficient Design Space Exploration Framework for FPGA Overlay Accelerators through Frequency Prediction and Bayesian Optimization

In edge AI inference, FPGA Overlay Accelerators offer superior performance-area balance but often lack accurate maximum frequency prediction and efficient Design Space Exploration (DSE) due to complex parameterization. To address these limitations, we propose a Bayesian optimization-based DSE framework using the Tree-Structured Parzen Estimator. We introduce a dependency-aware design space modeling (DAM) to prune the parameter space and a custom regression predictor (CREP) for frequency. To accommodate varying computational constraints, we present two implementations: a lightweight framework DEFA and an advanced framework DEFA-ML. DEFA saves computational cost of CREP and exploration runtime for rapid optimization. Conversely, DEFA-ML leverages a complex prediction model and a Large Language Model assistant for superior optimization quality. We validate the framework on the Altera FPGA AI Suite. For frequency prediction, DEFA provides fast and conservative predictions, while DEFA-ML achieves high linearity with a mean absolute percentage error of 4.21%. In throughput optimization, compared with the FPGA AI Suite baseline optimizer, DEFA improves throughput by 30.16% and DEFA-ML improves 35.12%. In area-throughput trade-off optimization, compared with the baseline, DEFA improves 39.05% and DEFA-ML improves 43.11% for single target model. For multiple target models, DEFA improves 40.76% and DEFA-ML improves 47.66%.