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Demonstrates improved synaptic transistor performance in neuromorphic computing, suggesting a scalable manufacturing method.
Charge-trapping thin-film transistor (CT-TFT) is a reliable structure for fabricating neuromorphic devices, owing to its non-volatile memory characteristics. However, the performance of charge-trapping synaptic transistors is critically limited by the requirement for high-quality tunnel layers, which typically rely on costly vacuum-based fabrication processes. Thus, developing a low-cost and scalable strategy for engineering tunneling interfaces remains a key challenge in neuromorphic electronics. In this work, an ultraviolet-ozone treatment was employed to grow, in situ, a dense and smooth alumina quasi-tunneling layer on a low-temperature annealed, solution-processed alumina charge-trapping layer. After the treatment, the alumina surface became smoother and exhibited significantly reduced defect density, leading to an increase in the Ion/off ratio from 104 to 106. The programming and light-assisted erasing properties of the resulting CT-TFTs were systematically evaluated under various applied voltages and light power densities. By modulating presynaptic action potential signals, typical synaptic behaviors were successfully simulated. Finally, a vision transformer-based neural network was employed to evaluate system-level performance, achieving a recognition accuracy of 89.5% on the classification of the Yale face image dataset. This work provides a simple and scalable route for engineering quasi-tunnel interfaces in oxide electronics and highlights their potential for low-cost, high-performance neuromorphic computing systems.
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Cui et al. (2026) studied this question.
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