Design and FPGA-Based Implementation of SCMA–DCSK Schemes for Reliable Communications

Sparse code multiple access (SCMA) is a promising non-orthogonal technique for enabling massive connectivity in future wireless networks. However, conventional SCMA detection methods often rely on the message passing algorithm, which is associated with high complexity and is not well suited for efficient hardware implementation. To address this limitation, two chaos-based SCMA communication schemes, namely SCMA-DCSK I and SCMA-DCSK II, are proposed along with their hardware implementation. In the first scheme, a high-dimensional sparse codebook based on orthogonal chaotic signals is introduced to enhance user separability and enable reliable detection using a simple comparator-based receiver. In the second scheme, quasi-orthogonal chaotic bases generated through cyclic shifting are employed to support index modulation, thereby improving spectral efficiency without increasing the modulation order. The proposed designs are implemented on a Xilinx Kintex-7 KC705 FPGA evaluation board using an FPGA-in-the-Loop (FIL) co-simulation framework. The hardware architecture is designed to provide efficient detection while preserving low resource utilization. Closed-form bit error rate (BER) expressions over an additive white Gaussian noise and Rayleigh channels are derived and verified through simulation. The BER, complexity, spectrum, and energy efficiency analyses demonstrate that the proposed schemes have highly improved SCMA-DCSK performance in various channel environments. The experimental results show a close match between theoretical, simulation, and hardware BER performance, demonstrating the feasibility of the proposed schemes for real-time multiuser communication systems.