Lateral and Vertical Scaling of <formula formulatype="inline"><tex Notation="TeX">In0.7 Ga0.3As</tex></formula> HEMTs for Post-Si-CMOS Logic Applications

In this paper, we have experimentally investigated the impact of lateral and vertical scaling ofIn0.7Ga0.3Ashigh-electron-mobility transistors (HEMTs) onto their logic performance. We have found that reducing theIn0.52Al0.48Asinsulator thickness results in much better electrostatic integrity and improved short-channel behavior down to a gate length of around 60 nm. Our nearly enhancement-mode 60-nm HEMTs featureVT = -0.02 V,DIBL = 93 mV/V,S = 88 mV/V, andION/ IOFF = 1.6 × 10⁴, atVDD = 0.5 V. We also estimate a gate delay ofCV/I = 1.6 psatVDD = 0.5 V. We have benchmarked these devices against state-of-the-art Si CMOS. For the same leakage current, which includes the gate leakage current, the InGaAs HEMTs exhibit1.2×more current drive(ION)than the state-of-the-art 65-nm low-power CMOS technology atVDD = 0.5 V.