In this paper, we report on the design, fabrication, packaging, and testing of very reliable CMOS-integrated 10-cm211-megapixel SiGe-based micromirror arrays on top of planarized six-level metal 0.18-¿m CMOS wafers. The array, which is to be used as a spatial light modulator (SLM) for optical maskless lithography, consists of 8 ¿m × 8 ¿m pixels, which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. Due to very stringent requirements on mounted-die flatness (2) is needed before mounting the SLM die on the holder. To enable this backside cleaning and to avoid front-side particles during dicing, handling, and wire bonding, a temporary waferor zero-level packaging cap, which can be placed and removed at room temperature, was developed. The dynamic white light interferometer measurements of packaged dies showed that 99.5% of the 123 648 mirrors tested are within the spec. In addition, a stable average cupping of below 7 nm, an rms roughness of below 1 nm, and a stable actuation of over 2.5 teracycles are demonstrated.
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Witvrouw et al. (2010) studied this question.
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