High‐uniformity polyimide liner was successfully achieved in through silicon vias with aspect ratio and density as high as 15:1 and 2.8 × 10 5 /cm 2 , respectively. The liner is deposited by vacuum‐assisted spin‐coating approach, which used vacuum treatment to fully fill the via followed by spin coating to achieve uniform liner. The uniformity along the sidewall of via is evaluated with cross‐sectional scanning electron microscopy images, and the results show that the thickness along sidewall from top to bottom has an average value of 530 nm and the achieved step coverage is above 33%. This liner deposition approach is completely compatible with complementary metal‐oxide‐ semiconductor (CMOS) processes, and exhibits excellent uniformity, demonstrating the potential of the proposed technique in future advanced three‐dimensional integration applications.
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Ding et al. (2016) studied this question.
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