Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts

High-level synthesis from OpenCL has shown significant potential, but current approaches conflict with mainstream OpenCL design methodologies owing to orders-of-magnitude longer field-programmable gate array compilation times and limited support for changing or adding kernels after system compilation. In this article, the authors introduce a back-end synthesis approach for potentially any OpenCL tool. This approach uses virtual coarse-grained reconfiguration contexts to speed up compilation by 4,211× at a cost of 1.8× system resource overhead, while also enabling 144× faster reconfiguration to support different kernels and rapid changes to kernels.