Waferscale Network Switches

In spite of being a key determinant of latency, cost, power, space, and capability of modern computer systems, network switch radix has not seen much growth over the years due to poor scaling of off-chip input/output pitches and switch die sizes. In this work, we show that one could use waferscale integration as a way to dramatically increase the size of the switch substrate and build a network switch with 32× higher radix than state-of-the-art network switches. We identified and addressed the limitations of internal bandwidth, external bandwidth, and power density, as the vanilla design would make the benefits of waferscale network switch minimal. We show that the waferscale network switch can be used to enable new computing systems, such as single-switch data centers and massive-scale singular GPUs. It can also lead to a dramatic reduction in data center network costs.