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An all-digital fast-locked synchronous duty-cycle corrector is presented. It corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The proposed circuit has been fabricated in a 0.18-mum CMOS technology. The measured duty-cycle error is between 1.5% and -1.4% for the input duty cycle of 40%~60%. The measured peak-to-peak jitter is 12.9ps at 1GHz. The measured operation frequency range is from 0.8GHz to 1.2 GHz
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Kao et al. (2006) studied this question.
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