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A hardware accelerator for 3D ren&ring, based on a mcdifkd scanline algorithm, is presented. The accelerator renders multiple scanlines in parallel with high efficiency, and is optimized for integration into systems that suppr[ high speed data streams (such as video). The architecture has a very high performance/cost ratio, but maintains a low entry cost and a high degree of scalability -key issues for incorporation in personal computers. The performance of both the general algorithm and the prototype implementation is analyzed.
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Kelley et al. (1992) studied this question.
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