Threshold voltage of excimer-laser-annealed polycrystalline silicon thin-film transistors

Based on experimental studies of n-channel excimer-laser-annealed polycrystalline silicon thin-film transistors with gate ratio width/length varying from 0.5 to 2.5, we propose a reliable method to determine the threshold voltage Vt from linear extrapolation of the transconductance to zero. The results reveal that the determined values of Vt are independent of the device geometry and the applied drain voltage in the linear region, in contrast with the drain current linear extrapolation method. The values of Vt are correlated with the density of the total trap states derived from the subthreshold gate swing voltage.