Generalised transformerless ultra step‐up DC–DC converter with reduced voltage stress on semiconductors

A non‐isolated DC–DC converter with high‐voltage gain and low‐voltage stress across the semiconductors is proposed in this study. The proposed converter consists of n stages of diode–capacitor–inductor ( D–C–L ) units at the input side and m units of voltage multiplier cells (VMCs) at the output side. Increasing of D–C–L units and VMCs, lead to high‐voltage gain at low duty cycle. Lower values of duty cycle will result in increasing of converter controllability and increasing of operation region. Also by increasing of VMCs, the voltage stress across the main switch and other semiconductors is reduced severely. Decreasing of voltage stress across the main switch leads to use a switch with lower R DS‐ON that reduces on state losses of the proposed converter. Besides, by decreasing of voltage stress across the diode rectifiers, diodes with less forward voltage drop can be adopted. The circuit performance will be compared with other solutions that were previously proposed for voltage step‐up in the terms of voltage gain, main switch voltage stress and number of components. Finally, a 357 V–65.5 W laboratory prototype with 92% conversion efficiency is built in order to prove the satisfying operation of the proposed converter and carried mathematical analysis.