Double and triple charge pump for power IC: dynamic models which take parasitic effects into account

An optimized design methodology for the double and triple charge pump is proposed. The circuits discussed given an output voltage greater than the supply voltage and are commonly used to power 1C or memory to allow the switching on of an MOS device. Theoretical models of charge pumps in the transient region are given. The models take parasitic capacitances and current leakage into account. They allow better knowledge of the circuit dynamics to be obtained and an optimized design to be achieved.>