Dual basis digit serial GF(2m) multiplier

A new digit serial GF(2 m ) multiplier based on the dual basis representation is presented for the first time in this paper. The multiplier is suitable for large word lengths such as those found in cryptosystems. Digit serial computations give a much better trade-off between area and speed in comparison with bit-parallel realization, which is too costly, and bit-serial realization which is too slow. The new multiplier is based on a look-ahead technique which serves to overcome the recursive algorithm used to calculate the extra elements of the operand represented in the dual basis prior to the multiplication process. This recursive algorithm is the main bottleneck for digit-serial multiplication. Unlike existing design, the new multiplier has low latency, and its digit size is not restricted by the type of primitive polynomial being used. A systolic version of the new multiplier, suitable for VLSI implementation, is also presented.