The proposed low-complexity ECG delineation and arrhythmia classification system offers a promising, power-efficient solution for future wearable ECG monitoring devices.
This paper presents a system for electrocardiogram (ECG) delineation and arrhythmia classification. The proposed system consists of a front-end integrated circuit, a delineation algorithm implemented on an FPGA board, and an arrhythmia classification algorithm. The front-end circuit applies a ternary second-order Delta modulator to measure the slope variation of the input analog ECG signal. The circuit converts the analog inputs into a pulse density modulated bitstream, whose pulse density is proportional to the slope variation of the input analog signal regardless of the instantaneous amplitude. The front-end chip can detect the minimum slope variation of 3. 2 mV/ms²within a 3 ms timing error. The front-end integrated circuit was fabricated with a 180 nm CMOS process occupying a 0. 25 mm²area with a 151 nW power consumption at the sampling rate of 1 kS/s. Based on the slope variation obtained from the front-end circuit, a delineation algorithm is designed to detect fiducial points in the ECG waveform. The delineation algorithm was tested on a Spartan-6 FPGA. The delineation system can detect the intervals, slopes, and morphology of the QRS/PT waves and form a feature set that contains 22 features. Based on these features, a rotate linear kernel support vector machine (SVM) is applied for patient-specific arrhythmia classification of the ventricular ectopic beat (VEB), supraventricular ectopic beat (SVEB), and heartbeats originating in sinus node. The performance of the proposed system is comparable to the recently published methods while providing a promising solution for the low-complexity implementation of future wearable ECG monitoring systems.
Tang et al. (Mon,) studied this question.