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A superconductive demultiplexer was designed, simulated, and tested as an interface between ultra-fast superconductive circuits and slower room-temperature electronics. The modular RSFQ shift-and-dump circuit was designed as a register of Non-Destructive Read-Out (NDRO) cells, which are timed by pulses from the system clock. Data is read out from a 1:N demultiplexer every N clock periods by applying a read-out pulse to the register's NDRO input. Circuit simulations and results for the successful experimental test of a 2-stage demultiplexer will be discussed.>
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Kaplan et al. (1995) studied this question.
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