Silicon Selective Epitaxial Growth and Electrical Properties of Epi/Sidewall Interfaces

Facet formation and stacking fault generation in silicon selective epitaxial growth are studied. On selective epilayer surfaces, a {311} facet and a {111} microfacet are formed on a {100} and a {111} substrate, respectively. In selective epilayers, stacking faults are observed adjacent to the sidewall Facet-free and stacking-fault-free selective epilayers are obtained using the <100>-orinted sidewall at low growth temperatures. These results are explained by an epitaxial growth model at hollow bridge sites. Electrical properties of the interfaces between the selective epilayer and the sidewall are also studied. The <100>-oriented SiO 2 sidewall has better electrical characteristics than other sidewall orientations and sidewall materials.