CMOS pipelined A/D convertor using current divider

A novel dynamic current divider based1 CMOS pipelined A/D convertor principle is presented. A basic successive approximation scheme is applied, thus the signal is not modified (i.e successively multiplied by two) along the A/D conversion. Consequently the most important speed limitation is the time to achieve the successive comparisons, which is lower than the time for signals to settle within 1/2 LSB in multiplying schemes2.3