Optimized reduced sample rate sigma-delta modulation

An optimized reduced sample rate sigma-delta modulation technique for application in digital to analog conversion is presented. A general framework of a sigma-delta modulating topology where the major arithmetic computation is done at a rate of an integer fraction of the bit-stream rate Is proposed and analyzed. The effectiveness of the technique is illustrated using simulations of second- and third-order sigma-delta modulators. Its impact on modulator complexity, stability, and performance is discussed. Optimization techniques such as quadratic programming are utilized in choosing proper filter coefficients.