The electrical properties of metal/ferroelectric/insulator/semiconductor (MFIS) structures with various insulators were investigated. Layers of Si 3 N 4 /SiO 2 (NO) formed by thermal oxidation and low pressure chemical vapor deposition (LPCVD) and Al 2 O 3 layers deposited by atomic layer deposition (ALD) were used as inter-dielectric layers. SrBi 2 Ta 2 O 9 (SBT) films used as ferroelectric layers were prepared by metal organic decomposition (MOD). The capacitance-voltage ( C – V ) curves including the memory window were affected by varying the annealing temperature for SBT films. Memory windows for MFIS structures with NO inter-dielectrics in the range of 0.75–1.2 V were maintained up to annealing temperatures of 900°C. The width of the memory window in C – V curves for MFISs using thin Al 2 O 3 layers decreases with increasing annealing temperature. Therefore, the selection of a good insulator and parameter control are required for the use of MFIS-ferroelectric random access memories (FRAMs).
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Lee et al. (1999) studied this question.
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