Computer-Aided Device Optimization for MOS/VLSI

Using a combination of computer-aided and experimental techniques, MOS/VLSI short-channel device optimization is demonstrated. Eleven different channeI doping profiles are investigated using both single-implant and double-implant approaches. A short channel model is introduced and, in conjunction with SUPREM process simulations, used to make a priori dose adjustments to achieve a common threshold voltage for all eleven implant situations. For NMOS silicon-gate structures with 500-/spl Aring/gate oxides and 0.65-/spl mu/m arsenic junctions, a 110-keV single implant provided optimum punch-through protection for channel lengths down to about 1.7 /spl mu/m. A double implant (40 keV shallow, 150 keV deep), gave slightly improved punchthrough protection at the expense of substantially increased substrate sensitivity. It is proposed that the optimum implant may provide balanced protection against surface and subsurface (bulk) punchthrough.