Investigation of threshold voltage instability induced by gate bias stress in ZnO nanowire field effect transistors

We investigated the threshold voltage instability induced by gate bias (V(G)) stress in ZnO nanowire (NW) field effect transistors (FETs). By increasing the V(G) sweep ranges and repeatedly measuring the electrical characteristics of the ZnO NW FETs, the V(G) stress was produced in the dielectric layer underneath the ZnO NW. Consequently, the electrical conductance of the ZnO NW FETs decreased, and the threshold voltage shifted towards the positive V(G) direction. This threshold voltage instability induced by the V(G) stress is associated with the trapping of charges in the interface trap sites located in the ZnO NW-dielectric interface. Our study will be helpful for understanding the stability of ZnO NW FETs during repetitive operations.