Characterisation of vertical gate-all-around tunnel FET using modulation-doped InGaAs nanowire/Si junction on SOI wafer

Tunnel field-effect transistors (TFETs) utilising quantum tunnel transport are expected as promising candidates for low-power switching applications, primarily due to their potential to overcome the thermionic limit of 60 mV/dec in subthreshold slope (SS) of conventional FETs. Despite this potential for low-voltage switching operation, TFETs face serious challenges for practical circuit integration, most notably low on-state currents and a narrow gate voltage window for maintaining steep SS characteristics. In this report, we characterised selective-area growth of modulation-doped core-multishell (CMS) nanowires (NWs) consisting of an InGaAs/InP/AlInAs/δ-doped AlInAs/AlInAs/InGaAs heterostructure on InGaAs NW sidewalls on silicon-on-insulator (SOI) substrates and vertical gate-all-around (VGAA) TFETs using the CMS NW-channels on SOI. The TFET devices exhibited robust gate modulation of the tunnelling current at the n-InGaAs/p-SOI junction, achieving a minimum SS of 35 mV/dec at a low drain-source voltage. While the TFETs are promising, the enhancement of the on-state current was constrained by an unintentionally thick InP barrier layer and over-etching to reveal the contact layer, both of which induce a non-ideal distribution of the internal electrical field. These findings underscored that precise dimensional control of the CMS architecture and moderate junction engineering at the InGaAs/Si heterointerface were critical for achieving high-performance VGAA-TFETs in practical applications.