Hybrid CMOS–SiNW FET Logic-Locking Architecture with Adaptive Key-Gate Mapping for Hardware Security

The rapid globalization of semiconductor manufacturing has increased the risk of intellectual property (IP) theft, reverse engineering, and malicious hardware tampering. Traditional CMOS-only logic-locking approaches suffer from predictable key-gate patterns, vulnerability to SAT-based attacks, and increased power–area overhead. To address these limitations, this work presents a Hybrid CMOS–SiNW FET Logic-Locking Architecture integrated with an Adaptive Key-Gate Mapping Engine, leveraging the compact gate-electrostatics and enhanced transistor-level tunability of Silicon-Nanowire Field-Effect Transistors (SiNW-FETs). The proposed method embeds evolvable XOR–XNOR encryption gates co-implemented in 14-nm CMOS and 10-nm SiNW-FET technology nodes, dynamically selected based on controllability, observability, entropy, and power-side channel vulnerability metrics. Experimental results on ISCAS-85 and ITC-99 benchmarks reveal that the hybrid locking framework achieves 6.8× higher SAT-attack resistance, 38% improvement in key-space obfuscation entropy, 22.6% reduction in power overhead, and 19.4% lower area penalty compared to conventional CMOS-only locking. Chip-level simulation in TCAD indicates secure operation under voltage and temperature variation with a measured 45% improvement in side-channel leakage immunity due to SiNW-FET electrostatic confinement. The architecture introduces a post-silicon adaptive re-mapping capability, complicating oracle-guided and removal attacks. Results demonstrate that hybrid CMOS–SiNW logic-locking enables ultra low cost, power efficient, and resilient hardware security, making it suitable for secure IoT SoCs, military-grade processors, and FPGA-based cryptographic units.