Modeling Resistance Instabilities of Set and Reset States in Phase Change Memory With Ge-Rich GeSbTe

To satisfy the growing market demand for embedded nonvolatile memory, alternative solutions to Flash technology are currently under investigation. Among these, phase change memory (PCM) is attracting strong interest due to the low cost of integration with the CMOS front-end and good scalability. Embedded PCM, however, must feature high reliability during both packaging and functional stages. This paper studies reliability of PCM based on Ge-rich GeSbTe, providing evidence for resistance drift and decay in both the reset and set states. Set-state instability is attributed to grain-boundary relaxation and grain growth. A unified model is presented, capable of predicting the reliability of set/reset states at elevated temperature.