The research reported in this paper is based on an approach to low-temperature/low-thermal budget device fabrication that combines plasma and rapid thermal processing, and which has been customized to control separately i) the N-atom bonding chemistry and composition profiles, and ii) the structural and chemical relaxations in stacked gate structures. Control of N-atom incorporation at the monolayer level at the crystalline- and polycrystalline-Si interfaces, and at alloy levels within the bulk dielectrics has been achieved by combining low-temperature (∼300° C) plasma-assisted processes to generate the N-atom concentration profiles, with low-thermal-budget rapid thermal annealing (RTA) to promote chemical and structural relaxations that minimize defects and defect precursors. Device measurements indicate that N-atom incorporation improves reliability with respect to hot carrier degradation of field effect transistors.
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Lucovsky et al. (1995) studied this question.
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