Border trap characterization in amorphous indium-gallium-zinc oxide thin-film transistors with SiOX and SiNX gate dielectrics

We investigate the border traps in amorphous indium-gallium-zinc oxide thin-film transistors with SiOX and SiNX interfacial gate dielectrics. Border traps have been known as trapping centers of electronic carriers in field-effect transistors, and non-negligible hysteresis is observed in the bidirectional high-frequency capacitance-voltage curve with a slow ramp rate in both dielectric devices. From the gate voltage transient method and 1/f noise analysis, the spatially and energetically uniform trap distribution is obtained, and approximately four to five times higher border trap densities are extracted from SiNX dielectric devices than from the SiOX dielectric ones.