A Low Power Design for Sbox Cryptographic Primitive of Advanced Encryption Standard for Mobile End-Users

Most known Sbox Advanced Encryption Standard implementations aim at minimizing chip covered area or achieving high throughput, and usually power consumption is a secondary metric of their cost. However, the need for low power applications with strict chip covered area constrains is great especially in mobile devices. In this paper low power architectures in limited area resources are proposed for Sbox, the basic cryptographic primitive of AES. Those architectures support encryption and decryption operation modes. In our proposed implementations, retaining a small chip covered area cost, hardware techniques for low power design, such as re-ordering of the components, introduction of redundant hardware (ideal delay line), reducing the driving strength â fan out, and insertion of registers in highly unbalanced points of the circuit are applied. Therefore, our implementations do not only reduce power consumption by a large degree, but they also have good area properties and offer an advantageous power-delay-area product in comparison with other known Sbox implementations. These properties give to our system the advantage to support low power mobile devices in low area system environments.