Demystifying Memory Access Patterns of FPGA-Based Graph Processing Accelerators

This is the authors' abstract. We don't add key points for this paper.

Recent advances in reprogrammable hardware (e.g., FPGAs) and memory (e.g., DDR4, HBM) promise to solve performance problems inherent to processing like irregular memory access patterns on traditional hardware(e.g., CPU). While several of these graph accelerators were proposed in recent, it remains difficult to assess their performance and compare them on graph workloads and accelerator platforms, due to few open source and excessive implementation effort. In this work, we build on a simulation environment for graph processing, to make several existing accelerator approaches comparable. This us to study relevant performance dimensions such as partitioning schemes memory technology, among others. The evaluation yields insights into the and weaknesses of current graph processing accelerators along these, and features a novel in-depth comparison.