Agentic Artificial Intelligence Framework for Automated VLSI Physical Design Optimization

Modern very-large-scale-integration (VLSI) physical design (PD) has become a principal bottleneck in the semiconductor design cycle. Transforming a gate-level netlist into a manufacturable layout requires the coordinated tuning of hundreds of interdependent parameters across floorplanning, placement, clock-tree synthesis (CTS) and routing, where a single sub-optimal decision can cascade into timing, power or design-rule violations. Conventional design-space-exploration (DSE) methods—expert manual tuning, black-box Bayesian optimization and single-stage reinforcement learning (RL)—remain sample-inefficient and stage-local, and they cannot reason about why a configuration failed. This paper proposes an Agentic Artificial Intelligence framework in which a large-language-model (LLM) orchestrator coordinates a team of specialized, tool-augmented agents—one per PD stage—together with a critic/reflection agent and an episodic memory. The agents perceive quality-of-results (QoR) reports, reason over prior design points, invoke open-source EDA engines, and iteratively refine the flow toward a composite power–performance–area (PPA) objective. Evaluated on six open-source benchmarks in a 7-nm technology, the framework closes on average 93.5% of the worst-negative-slack gap, reduces total power by 21.4% and design-rule-check violations by 91% relative to the default flow, while requiring only 42 optimization iterations—a 3–5× improvement in sample efficiency over Bayesian and RL baselines. Ablation confirms that the planner, critic and memory modules each contribute materially. The results indicate that agentic, reasoning