Hole mobility enhancements in strained Si/Si1−yGey p-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si1−xGex (x<y) virtual substrates

We have achieved peak hole mobility enhancement factors of 5.15 over bulk Si in metal-oxide-semiconductor field-effect transistors (MOSFETs) by combining tensile strained Si surface channels and compressively strained 80% Ge buried channels grown on relaxed 50% Ge virtual substrates. To further investigate hole transport in these dual channel structures, we study the effects of strain, alloy scattering, and layer thickness on hole mobility enhancements in MOSFETs based upon these layers. We show that significant performance boosts can be obtained despite the effects of alloy scattering and that the best hole mobility enhancements are obtained for structures with thin Si surface layers.