Demonstrates improved image interpolation efficiency in real-time systems, suggesting enhanced performance scalability.
Image interpolation is a fundamental operation in real-time image processing systems, widely used in applications such as disaster monitoring, medical imaging, and industrial inspection. Despite its algorithmic simplicity, interpolation exhibits complex control flow, irregular memory access, and fine-grained data dependencies, which severely limit execution efficiency on conventional parallel architectures. Existing acceleration approaches predominantly rely on Graphics Processing Units (GPUs) under the Single Instruction Multiple Thread (SIMT) execution model. However, frequent branch divergence, irregular address generation, and low task granularity significantly degrade warp utilization and energy efficiency, making further performance scaling increasingly difficult. To address these challenges, this paper proposes an interpolation-oriented acceleration architecture based on a dataflow execution model. By rethinking interpolation computation from an execution-paradigm perspective, the proposed design enables fine-grained, data-driven parallelism without being constrained by rigid synchronization and execution groups. Specifically, we design customized vectorized data paths and instructions tailored to weighted interpolation computation, introduce a dataflow multitasking parallel mechanism that improves processing-element utilization through time-multiplexed task execution, and develop a double-buffered on-chip memory architecture to overlap computation with data movement. Experimental results demonstrate that the proposed approach reduces overall execution time by an average of 67.32% compared with the baseline dataflow implementation, while increasing processing-array utilization to 65.72%. The revised evaluation additionally compares DFU-I with both algorithm-matched hand-written CUDA kernels and NVIDIA NPP library kernels, reports measured GPU active power and energy per image, and provides a configuration-by-configuration power and energy ablation for the proposed architectural mechanisms.
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Zhang et al. (2026) studied this question.
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