Fabrication of III–V on Insulator Structures on Si Using Microchannel Epitaxy with a Two-Step Growth Technique

We report a new microchannel epitaxy (MCE) technique for forming III–V semiconductor on insulator (III–V-OI) structures on a Si substrate with a thermally oxidized SiO 2 mask for high performance n-type metal–insulator–semiconductor field-effect transistors (MISFETs). To reduce dislocations and antiphase domains (APDs), we propose a novel fabrication method of forming III–V-OI structures, where a two-step growth method is combined with MCE. The growth temperature of the low-temperature buffer layers and the growth rate in the two-step growth are optimized to meet the competing requirements for the reduction in APDs and selective growth. We demonstrate a fabrication of high-quality GaAs-OI structures using our proposed growth method under an optimized growth condition.