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In this paper, a bandwidth and power scalable digital predistortion architecture is proposed for the linearization of power amplifiers (PA) exhibiting memory effects. The proposed digital predistorter allows for low complexity update following changes in the signal's bandwidth and/or power level. Experimental validation carried on a 300-W Doherty PA shows that the scalable predistorter architecture achieves similar performance as its conventional counterpart. However, the proposed predistorter requires the update of up to 50% less coefficients than the conventional predistorter.
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Hammi et al. (2013) studied this question.
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