100 GHz Parametric CMOS Frequency Doubler

A parametric MOS varactor-based integrated frequency doubler is reported. The circuit is implemented in 130 nm CMOS but uses a conservative 0.35 μm gate length and produces an output between 94 and 108 GHz with a minimum measured conversion loss of 14.5 dB and a maximum output power of -7.5 dBm. Slow-wave transmission line filters are employed to reduce circuit loss and the area required by the chip.