In this paper, we derive the discrete‐time model for the power‐factor‐correction (PFC) buck‐boost converter in terms of a stroboscopic switching map. Fast‐scale instability is analysed through a fold diagram, which exposes the periodicity of the operation as well as the locations of the critical phase angles of the line voltage at which instability begins to occur along a half‐line cycle. The asymmetrical locations of the critical phase angles along a half‐line cycle is explained in terms of ‘under‐developed’ bifurcation. Border collision bifurcations are observed and analysed in detail.
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Zou et al. (2006) studied this question.
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