The formation of a through-silicon via (TSV) enables three-dimensional (3D) interconnects for chip-stacking applications that will be especially important for integrating heterogeneous devices. Many processing steps are involved with the major areas including: via formation; deposition of via insulation, barrier, and Cu seed films; Cu electroplating for via-fill; wafer thinning; and backside processing. The via diameter is 4–8μm, via depth is 15–20μm, and a 20μm pitch is used in this study. Each step will be described in the process flow with the considerations discussed for successful process integration.
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Spiesshoefer et al. (2005) studied this question.
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