Modeling of VLSI RC parasitics based on the network reduction algorithm

This paper presents a method of modeling of R and C parasitics in VLSI circuits. A network representation is generated for finite difference discretization of 2-D Laplace's equation, and a reduction algorithm is applied to this network. The solution area can be defined by any set of polygons. If n is the number of discretization nodes the new algorithm is O(n/sup 1.5/). It yields directly the coefficients of capacitance or admittance matrix. In contrast to other methods, in the network reduction approach, the time required for modeling depends mainly upon the complexity of the solution area but weakly upon the number of terminals. This feature is particularly valuable in application to circuit extraction.>