Simulation study demonstrates robust optimization of a 45 nm CMOS low-noise amplifier using evolutionary algorithms, highlighting improved efficiency for wireless sensor networks.
Low-noise amplifiers (LNAs) are critical components of wireless sensor network (WSN) receivers, where high gain, low noise, low power consumption, and robust operation under process variations are essential. This study presents a variation-aware multi-objective optimization framework for a 45 nm CMOS LNA by integrating Latin Hypercube Sampling (LHS) with the Non-Dominated Sorting Genetic Algorithm III (NSGA-III). Process-induced variations in threshold voltage, channel length, oxide thickness, electron mobility, and gate capacitance are modeled using statistically representative LHS samples and incorporated directly into the optimization process. Four key RF performance metrics—noise figure (NF), voltage gain, power dissipation (PD), and third-order input intercept point (IIP3)—are optimized simultaneously. The optimized design achieves an NF of 1.32 dB, gain of 15.40 dB, PD of 0.59 mW, and IIP3 of 3.8 dBm, demonstrating substantial improvements over the baseline design. Additional RF validation through S-parameter, stability, noise figure, and two-tone intermodulation analyses confirms the practical effectiveness of the optimized LNA. The results show that the proposed LHS–NSGA-III framework can generate robust Pareto-optimal solutions under manufacturing uncertainties, providing an effective methodology for designing energy-efficient and reliable RF front-end circuits for emerging WSN and IoT applications.
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Sikarwar et al. (2026) studied this question.
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