Synapse
⌘+K
Synapse
PulseExploreClubsResearchersJournals
Instagram
HomeClubsExplore
May 1, 2002IEEE Journal of Solid-State Circuits

Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters

View Full Paper
Ask AI
Bookmark
Share

Authors

BFBrian FloydNorth Carolina State UniversityCHChih-Ming HungMediaTek (Taiwan)OKO K.K.The University of Texas at Dallas

Discussion

Loading...

Member takes

Implication

Key Points

Key points are not available for this paper at this time.

Cite This Study

Floyd et al. (2002) studied this question.

synapsesocial.com/papers/6a7f703bebb736a23490715dhttps://doi.org/10.1109/4.997846
View Full Paper
Ask AI
Bookmark
Share

Also Consider

Synapse has enriched 3 closely related papers on similar clinical questions. Consider them for comparative context:

  1. 1A packaged 1.1-GHz CMOS VCO with phase noise of -126 dBc/Hz at a 600-kHz offset2000 · 50 citations
  2. 2A 200-MHz CMOS phase-locked loop with dual phase detectors1989 · 98 citations
  3. 3High-speed CMOS circuit technique1989 · 794 citations