Origin of Soft-Switching Output Capacitance Loss in Cascode GaN HEMTs at High Frequencies

Output capacitance (COSS) loss (EDISS) is produced when theCOSSof a power device is charged and discharged, which ideally should be a lossless process. This loss was recently revealed to be a crucial concern for GaN high electron mobility transistors (HEMTs) in high-frequency soft-switching applications. Among various GaN devices, the composite-type, cascode GaN HEMT was reported to show the largestEDISSwith a voltage dependence distinct from discrete GaN HEMTs. However, the physical origins of theEDISSin cascode GaN HEMTs remain unclear. This article fills this gap by identifying three loss components and, for the first time, experimentally quantifying them in the multi-MHz resonant switching. These loss components include: a) the avalanche loss of Simosfet; b) the intrinsicEDISSof GaN HEMT; and c) the Si avalanche-induced GaN turn-onloss. The last component was found to dominateEDISSat high voltage. By eliminating the Si avalanche and the associated loss components (a) and (c), theEDISSof cascode GaN HEMTs can be reduced by up to 75% at the price of an increase in output charge and switching transition time. These results provide new physical insights and practical guidelines to trim the soft-switching loss of cascode GaN HEMTs in high-frequency applications.