Parallel Counters for Low-Pass Phase Modulation–Demodulation ADCs

The signal-to-noise ratio (SNR) of a low-pass phase modulation-demodulation analog-to-digital converter (LP PMD ADC) depends on the number of channels in its demodulator (synchronizer or race arbiter). For 3, 7, and 15 channels, this gives 9.5, 16.9, and 23.5 dB theoretical SNR gain in comparison to a single channel. We have designed a family of parallel counters that sums the unweighted outputs of each synchronizer channel to produce a binary code. A 7-to-3 counter that can be truncated into 3-to-2 and extended into 15-to-4 adders was fabricated using 10 and 20 kA/cm2MIT-LL processes and successfully tested. The completed designs of 1-, 3-, and 7-channel LP PMD ADC are also briefly discussed.