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Manufacturing tolerances influence circuit parameters, and inductance is no exception. A computer application was developed to fully automate inductance calculation as part of a layout extraction suite. InductEx takes a GDSII layout file as input, finds the inductance ports, extracts structures, applies mask-to-wafer offsets and random process tolerances to the circuit structures, builds deck files that can be processed with FastHenry, and manages FastHenry-all autonomously. Results are presented for the simulated variation in inductance-both self and mutual, over hundreds of runs-in several common RSFQ structures in the Hypres 1 kA/cm/sup 2/ process (with the latest tolerance values built in), even with the presence of moats.
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Fourie et al. (2005) studied this question.
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